Edinburgh Napier University

Automated synthesis and optimization of multilevel logic circuits

Dates:

1997 to 2001
Qualification:

Doctorate (PhD)

Project Team

Automated synthesis and optimization of multilevel logic circuits

Lingli Wang

Automated synthesis and optimization of multilevel logic circuits

Abid Almaini

Automated synthesis and optimization of multilevel logic circuits

Prof Bill Buchanan

Professor
School of Computing Engineering and the Built Environment

B.Buchanan@napier.ac.uk

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