Citation
Guan, Z., Thomson, P. & Almaini, A. E. A. (1994). Parallel CMOS 2's complement multiplier based on 5:3 counter. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., 298-301. doi:10.1109/ICCD.1994.331910. ISBN 0-8186-6565-3
Authors
Keywords
Integrated circuits; CMOS; Computing; Parallel processing; Tree structures; VLSI circuits;
Monthly Views: