Integrating and extending JCSP.
Conference Proceeding
Welch, P., Brown, N., Moores, J., Chalmers, K., & Sputh, B. (2007)
Integrating and extending JCSP. In A. McEwan, S. Schneider, W. Ifill, & P. Welch (Eds.), Communicating Process Architectures 2007, 349-370
This paper presents the extended and re-integrated JCSP library of CSP packages for Java. It integrates the differing advances made by Quickstone's JCSP Network Edition and th...
On balancing network traffic in path-based multicast communication
Journal Article
Al-Dubai, A., Ould-Khaoua, M., & Mackenzie, L. (2006)
On balancing network traffic in path-based multicast communication. Future Generation Computer Systems, 22(7), 805-811. doi:10.1016/j.future.2006.02.009
This paper presents a new multicast path-based algorithm, referred to here as the Qualified Groups (QG for short), which can achieve a high
degree of parallelism and low commu...
Algorithms in computer-aided design of VLSI circuits.
Thesis
Yang, M. Algorithms in computer-aided design of VLSI circuits. (Thesis)
Edinburgh Napier University. Retrieved from http://researchrepository.napier.ac.uk/id/eprint/6493
With the increased complexity of Very Large Scale Integrated (VLSI) circuits,
Computer Aided Design (CAD) plays an even more important role. Top-down
design methodology and la...
Workplace soundscape mapping: a trial of Macaulay and Crerar’s method
Conference Proceeding
McGregor, I., Crerar, A., Benyon, D., & LePlâtre, G. (2006)
Workplace soundscape mapping: a trial of Macaulay and Crerar’s method. In Proceedings of the 12th International Conference on Auditory Display (ICAD2006)
This paper describes a trial of Macaulay and Crerar’s method of mapping a workplace soundscape to assess its fitness as a basis for an extended soundscape mapping method. Twel...
A novel low power FSM partition approach and its implementation.
Journal Article
Xia, Y., Ye, X., Wang, L. Y., Tao, J., & Almaini, A. E. A. (2005)
A novel low power FSM partition approach and its implementation. NORCHIP Conference, 102-105. https://doi.org/10.1109/NORCHP.2005.1596999
A new Finite State Machine (FSM) partioning approach is proposed in this paper. A genetic algorithm (GA) is employed to search the optimal or near optimal solution. A new cost...
FPGA placement using genetic algorithm with simulated annealing.
Journal Article
Yang, M., Almaini, A. E. A., Wang, L. Y. & Wang, P. (2005)
FPGA placement using genetic algorithm with simulated annealing. ASICON. 2, 808-811. doi:10.1109/ICASIC.2005.1611450
A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the f...
A novel multiple-valued CMOS flip-flop employing multiple-valued clock.
Journal Article
Xia, Y., Wang, L. Y. & Almaini, A. E. A. (2005)
A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology. 20, 237-242. doi:10.1007/s11390-005-0237-4. ISSN 1000-9000
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with tr...
Evolutionary algorithms and their use in the design of sequential logic circuits.
Journal Article
Ali, B., Almaini, A. E. A. & Kalganova, T. (2004)
Evolutionary algorithms and their use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines. 5, 11-29. doi:10.1023/B:GENP.0000017009.11392.e2. ISSN 1389-2576
In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed meth...
Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion.
Journal Article
Cheng, J., Chen, X., Faraj, K. & Almaini, A. E. A. (2003)
Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. IEE proceedings. Computers and digital techniques. 150, 397-402. doi:10.1049/ip-cdt:20030969. ISSN 1350-2387
Based on the features of coincidence operation, a canonical OR coincidence (COC) expansion of logical functions in the OR-coincidence algebraic system is proposed, and its map...
Differential CMOS edge-triggered flip-flop with clock gating.
Journal Article
Xia, Y. & Almaini, A. E. A. (2002)
Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters. 38, 9-11. doi:10.1049/el:20020038. ISSN 0013-5194
A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design ...