McGregor, I. (2018)
This book explores the underlying principles of sound design for linear and interactive media, and specifically how they apply to theatre. The focus of the text is about how t...
Modelling and Characterization of NAND Flash Memory Channels.
Xu, Q., Gong, P., Chen, T. M., Michael, J., & Li, S. (2015)
Modelling and Characterization of NAND Flash Memory Channels. Measurement : journal of the International Measurement Confederation, 70, 225-231. https://doi.org/10.1016/j.measurement.2015.04.003
The threshold voltage distribution after ideal programming in NAND flash memory cells is usually distorted by a combination of the random telegraph noise (RTN), cell-to-cell I...
Computer aided synthesis and optimisation of electronic logic circuits
Al-Jassani, B. A. Computer aided synthesis and optimisation of electronic logic circuits. (Thesis)
Edinburgh Napier University. Retrieved from http://researchrepository.napier.ac.uk/id/eprint/6658
In this thesis, a variety of algorithms for synthesis and optimisation of combinational and sequential logic circuits are developed. These algorithms could be part of new comm...
The VoIP intrusion detection through a LVQ-based neural network.
Presentation / Conference
Zheng, L., & Peng, T. (2009, November)
The VoIP intrusion detection through a LVQ-based neural network. Paper presented at The 4th International Conference for Internet Technology and Secured Transactions, London, UK
Being a fast-growing Internet application, Voice over Internet Protocol shares the network resources with the regular Internet traffic. However it is susceptible to the existi...
FPGA placement using genetic algorithm with simulated annealing.
Yang, M., Almaini, A. E. A., Wang, L. Y. & Wang, P. (2005)
FPGA placement using genetic algorithm with simulated annealing. ASICON. 2, 808-811. doi:10.1109/ICASIC.2005.1611450
A mixed Genetic Algorithm and Simulated Annealing (GASA) algorithm is used for the placement of symmetrical FPGA. The prpoposed algortithm includes 2 stage processes. In the f...
A novel multiple-valued CMOS flip-flop employing multiple-valued clock.
Xia, Y., Wang, L. Y. & Almaini, A. E. A. (2005)
A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology. 20, 237-242. doi:10.1007/s11390-005-0237-4. ISSN 1000-9000
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with tr...
Evolutionary algorithms and their use in the design of sequential logic circuits.
Ali, B., Almaini, A. E. A. & Kalganova, T. (2004)
Evolutionary algorithms and their use in the design of sequential logic circuits. Genetic Programming and Evolvable Machines. 5, 11-29. doi:10.1023/B:GENP.0000017009.11392.e2. ISSN 1389-2576
In this paper an approach based on an evolutionary algorithm to design synchronous sequential logic circuits with minimum number of logic gates is suggested. The proposed meth...
Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion.
Cheng, J., Chen, X., Faraj, K. & Almaini, A. E. A. (2003)
Expansion of logical function in the OR-coincidence system and the transform between it and maxterm expansion. IEE proceedings. Computers and digital techniques. 150, 397-402. doi:10.1049/ip-cdt:20030969. ISSN 1350-2387
Based on the features of coincidence operation, a canonical OR coincidence (COC) expansion of logical functions in the OR-coincidence algebraic system is proposed, and its map...
Differential CMOS edge-triggered flip-flop with clock gating.
Xia, Y. & Almaini, A. E. A. (2002)
Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters. 38, 9-11. doi:10.1049/el:20020038. ISSN 0013-5194
A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design ...
Reversed ROBDD circuits.
Bystrov, A. & Almaini, A. E. A. (1998)
Reversed ROBDD circuits. Electronics Letters. 34, 1447-1449. doi:10.1049/el:19981070. ISSN 0013-5194
A new class of logic circuits is proposed. Being derived from reduced ordered binary decision diagrams, these circuits inherit compactness and the ability to represent very la...