Research Output

A novel multiple-valued CMOS flip-flop employing multiple-valued clock.

  A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterised by improved storage capacity, flexible logic structure and reduced power dissipation.

  • Type:

    Article

  • Date:

    28 February 2005

  • Publication Status:

    Published

  • Publisher

    Springer

  • DOI:

    10.1007/s11390-005-0237-4

  • ISSN:

    1000-9000

Citation

Xia, Y., Wang, L. Y. & Almaini, A. E. A. (2005). A novel multiple-valued CMOS flip-flop employing multiple-valued clock. Journal of Computer Science and Technology. 20, 237-242. doi:10.1007/s11390-005-0237-4. ISSN 1000-9000

Authors

Keywords

Integrated circuits; CMOS; Flip-flop circuits; Multiple-valued clock; Computer systems; Computer logic; Performance evaluation;

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