Research Output

Differential CMOS edge-triggered flip-flop with clock gating.

  A non-redundant transition clock chain is proposed and applied to differential edge-triggered flip-flops. PSPICE simulation shows that compared to a recently published design the proposed circuit can save power when switching activity of the input signal

  • Type:

    Article

  • Date:

    03 January 2002

  • Publication Status:

    Published

  • Publisher

    Institution of Engineering and Technology

  • DOI:

    10.1049/el:20020038

  • ISSN:

    0013-5194

Citation

Xia, Y. & Almaini, A. E. A. (2002). Differential CMOS edge-triggered flip-flop with clock gating. Electronics Letters. 38, 9-11. doi:10.1049/el:20020038. ISSN 0013-5194

Authors

Keywords

CMOS integrated circuits; Flip-flops; Edge-trigger; PSPICE simulation; Power saving;

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