Research Output

Parallel CMOS 2's complement multiplier based on 5:3 counter.

  A parallel 8x8 2's complement multiplier based on a novel 5:3 counter is presented. The structure of the multiplier is simple, regular and very suitable for VLSI implementation. Compared with Wallace tree and Redundant Bimary Addition Tree, the proposed scheme requires less levels for the same number of partial products, resulting in a simpler and faster circuit.

  • Date:

    30 September 1994

  • Publication Status:

    Published

  • Publisher

    IEEE

  • DOI:

    10.1109/ICCD.1994.331910

  • Library of Congress:

    QA75 Electronic computers. Computer science

Citation

Guan, Z., Thomson, P. & Almaini, A. E. A. (1994). Parallel CMOS 2's complement multiplier based on 5:3 counter. In IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD '94. Proceedings., 298-301. doi:10.1109/ICCD.1994.331910. ISBN 0-8186-6565-3

Authors

Keywords

Integrated circuits; CMOS; Computing; Parallel processing; Tree structures; VLSI circuits;

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