Research Output
A GALS Infrastructure for a Massively Parallel Multiprocessor
  This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency.

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  • Date:

    08 October 2007

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  • Publisher

    Institute of Electrical and Electronics Engineers (IEEE)

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  • Funders:

    Engineering and Physical Sciences Research Council


Plana, L. A., Furber, S. B., Temple, S., Khan, M., Shi, Y., Wu, J., & Yang, S. (2007). A GALS Infrastructure for a Massively Parallel Multiprocessor. IEEE Design and Test of Computers, 24(5), 454-463.


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