Building a Reusable and Extensible Automatic Compiler Infrastructure for reconfigurable devices

Research Output

Multi-Level Intermediate Representation (MLIR) is gaining increasing attention in reconfigurable hardware communities due to its capability to represent various abstract levels for software compilers. This project aims to be the first to provide an end-to-end framework that leverages open-source, cross-platform compilation technology to generate MLIR from SYCL. Additionally, it aims to explore a lowering pipeline that converts MLIR to RTL using open-source hardware intermediate representation (IR) and compilers. Furthermore, it aims to couple the generated hardware module with the host CPU using vendor-specific crossbars. Our preliminary results demonstrated the feasibility of lowering customized MLIR to RTL, thus paving the way for an end-to-end compilation.

Date:

02 November 2023
Publication Status:

Published
Publisher

IEEE
DOI:

10.1109/FPL60245.2023.00062
Funders:

Edinburgh Napier Funded

http://researchrepository.napier.ac.uk/output/3133934 <p>Zang, Z., Dolinsky, U., Ghiglio, P., Cherubin, S., Goli, M., & Yang, S. (2023). Building a Reusable and Extensible Automatic Compiler Infrastructure for reconfigurable devices. In <i>2023 33rd International Conference on Field-Programmable Logic and Applications (FPL)</i> (351-352). https://doi.org/10.1109/FPL60245.2023.00062</p>

Citation

Zang, Z., Dolinsky, U., Ghiglio, P., Cherubin, S., Goli, M., & Yang, S. (2023). Building a Reusable and Extensible Automatic Compiler Infrastructure for reconfigurable devices. In 2023 33rd International Conference on Field-Programmable Logic and Applications (FPL) (351-352). https://doi.org/10.1109/FPL60245.2023.00062