Research Output

Low Power Design Techniques for Digital Logic Circuits.

  With the rapid increase in the density and the size of chips and systems, area and power dissipation
become critical concern in Very Large Scale Integrated (VLSI) circuit design. Low power
design techniques are essential for today's VLSI industry. The history of symbolic logic and some
typical techniques for finite state machine (FSM) logic synthesis are reviewed.
The state assignment is used to optimize area and power dissipation for FSMs. Two cost
functions, targeting area and power, are presented. The Genetic Algorithm (GA) is used to search
for a good state assignment to minimize the cost functions. The algorithm has been implemented
in C. The program can produce better results than NOVA, which is integrated into SIS by DC
Berkeley, and other publications both in area and power tested by MCNC benchmarks.
Flip-flops are the core components of FSMs. The reduction of power dissipation from flip-flops
can save power for digital systems significantly. Three new kinds of flip-flops, called differential
CMOS single edge-triggered flip-flop with clock gating, double edge-triggered and multiple valued
flip-flops employing multiple valued clocks, are proposed. All circuits are simulated using PSpice.
Most researchers have focused on developing low-power techniques in AND/OR or NAND
& NOR based circuits. The low power techniques for AND /XOR based circuits are still in
their early stage of development. To implement a complex function involving many inputs,
a form of decomposition into smaller subfunctions is required such that the subfunctions fit
into the primitive elements to be used in the implementation. Best polarity based XOR gate
decomposition technique has been developed, which targets low power using Huffman algorithm.
Compared to the published results, the proposed method shows considerable improvement in
power dissipation. Further, Boolean functions can be expressed by Fixed Polarity Reed-Muller
(FPRM) forms. Based on polarity transformation, an algorithm is developed and implemented
in C language which can find the best polarity for power and area optimization. Benchmark
examples of up to 21 inputs run on a personal computer are given.

  • Type:

    Thesis

  • Date:

    28 February 2003

  • Publication Status:

    Unpublished

  • Library of Congress:

    TK Electrical engineering. Electronics Nuclear engineering

  • Dewey Decimal Classification:

    621.381 Electronics

Citation

Xia, Y. Low Power Design Techniques for Digital Logic Circuits. (Thesis)

Keywords

Very Large Scale Integrated (VLSI) circuit design; symbolic logic; finite state machine (FSM) logic synthesis; poer dissipation;

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