Research Output
A Low Power Sigma-Delta Modulator with Hybrid Architecture
  Analogue-to-digital converters (ADC) using oversampling technology and Σ-∆ modulation mechanism are widely applied in digital audio systems. This paper presents an audio modulator with high accuracy and low power consumption by using discrete second-order feedforward structure. A 5-bit SAR (Successive-approximation-register) quantizer is integrated into the chip, which reduces the number of comparators and the power consumption of the quantizer compared with Flash ADC type quantizers. An analogue passive adder is used to sum the input signals and it is embedded in a SAR ADC composed of capacitor array and a dynamic comparator which has no static power consumption. To validate the design concept, the designed modulator is developed in a 180 nm CMOS process. The peak SNDR (signal to noise distortion ratio) is calculated as 106 dB and the total power consumption of the chip is recorded as 3.654 mW at the chip supply voltage of 1.8 V. The input sine wave of 0 to 25 kHz is sampled at a sampling frequency of 3.2 Ms/s. Moreover, the results achieve 16-bit ENOB (effective number of bits) when the amplitude of the input signal is varied between 0.15 V to 1.65 V. By comparing with other modulators which were realized by 180nm CMOS process, the proposed architecture outperforms with lower power consumption.

  • Type:


  • Date:

    16 September 2020

  • Publication Status:


  • DOI:


  • Funders:

    National Natural Science Foundation of China


An, S., Xia, S., Ma, Y., Ghani, A., See, C. H., Abd-Alhameed, R. A., …Yang, R. (2020). A Low Power Sigma-Delta Modulator with Hybrid Architecture. Sensors, 20(18),



Feedforward modulator, quantizer, SAR, Σ-Δ modulator

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