Edinburgh Napier University

  This paper proposes a new solution to improve the performance parameters of on-chip antenna designs on standard CMOS silicon technology. The proposed method is based on applying the metasurface technique and exciting the radiating elements through coupled feed mechanism. The on-chip antenna is constructed from three layers comprising silicon-ground-silicon layers, so that the ground plane has sandwiched between two silicon layers. The silicon and ground-plane layers have thicknesses of 20μm and 5μm, respectively. The 3×3 array consisting of the asterisk-shaped radiating elements has implemented on the top silicon layer by applying the metasurface approach. Three slot lines in the ground-plane are modelled and located directly under
the radiating elements. The radiating elements are excited through the slot-lines using an open-circuited microstrip-line constructed on the bottom silicon layer. The proposed method to excite the structure is based on the coupled feeding mechanism. In addition, by the proposed feeding method the on-chip antenna configuration supresses the substrate losses and surface-waves. The antenna exhibits a large impedance bandwidth of 60GHz from 0.5THz to 0.56THz with an average radiation gain and efficiency of 4.58dBi and 25.37%, respectively. The proposed structure has compact dimensions of 200×200×45μm3. The results shows that, the proposed technique is therefore suitable for on-chip antennas for applications