Research Output
Reconfigurable neurons - making the most of configurable logic blocks (CLBs)
  An area-efficient hardware architecture is used to map fully parallel cortical columns on Field Programmable Gate Arrays (FPGA) is presented in this paper. To demonstrate the concept of this work, the proposed architecture is shown at the system level and benchmarked with image and speech recognition applications. Due to the spatio-temporal nature of spiking neurons, this has allowed such architectures to map on FPGAs in which communication can be performed through the use of spikes and signal can be represented in binary form. The process and viability of designing and implementing the multiple recurrent neural reservoirs with a novel multiplier-less reconfigurable architectures is described.

  • Date:

    30 September 2015

  • Publication Status:

    Published

  • Publisher

    IEEE

  • DOI:

    10.1109/itecha.2015.7317451

  • Library of Congress:

    TK Electrical engineering. Electronics Nuclear engineering

  • Dewey Decimal Classification:

    621.38 Electronics & Communications engineering

  • Funders:

    Historic Funder (pre-Worktribe)

Citation

Ghani, A., See, C. H., Migdadi, H., Asif, R., Abd-Alhameed, R. A., & Noras, J. M. (2015). Reconfigurable neurons - making the most of configurable logic blocks (CLBs). https://doi.org/10.1109/itecha.2015.7317451

Authors

Keywords

recurrent neural networks, reservior computing, reconfigurable computing, FPGAs, neural signal processing

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